In modern integrated circuits, the speed at which an integrated circuit operates is generally limited, among other things, by the distance between the farthest separated components that communicate with each other on the chip. Laying out circuits as three-dimensional structures has been shown to significantly reduce the communication path length between on-chip components, provided the vertical distances between layers are smaller than the chip width of the individual layers. Thus, by stacking circuit layers vertically, the overall chip speed is typically increased. One method that has been used to implement such stacking is through wafer bonding.
Wafer bonding generally is the joining together of two or more semiconductor wafers on which integrated circuitry has been formed. Wafers are typically joined by direct bonding of external oxide layers or by adding adhesives to inter-level dielectric layers. The bonded result produces a three-dimensional wafer stack which is subsequently diced into separate stacked die, with each individual stacked die having multiple layers of integrated circuitry. In addition to the increased speed that the three-dimensional circuitry typically experiences, wafer stacking offers other potential benefits, including improved form factors, lower costs, and greater integration through system on chip (SOC) solutions. In order to enable the various components integrated within each stacked die, electrical connections between stacked dies are formed that provide conduction between the various components in the stacked dies. Such an electrical connection typically comprises through silicon vias (TSVs) formed in a die connecting to the underlying circuitry, and bonding pads that are metal areas formed on the front surface of a die. The bonding pads are electrically connected to the TSVs and have increased bonded area, thus facilitating the connections between stacked dies.
In general, bonding pads are slightly elevated from a surface of a die in order to perform desired bonding. After the bonding pads are formed on the dies, one of the dies is turned over so that its bonding pads are position over the corresponding bonding pads of a base die. The two dies may be pressed together and bonded using a typical thermal diffusion bonding process. The two dies may also be bonded together using an adhesive bonding process. Examples of such bonding methods are described in U.S. Pat. No. 6,642,081 to Patti (hereinafter Patti) and U.S. Pat. No. 6,897,125 to Morrow, et al., (hereinafter Morrow). Patti describes forming bonding by a thermal diffusion bonding process, while Morrow describes forming wafer bonding using a thermal diffusion bonding process or an adhesive bonding process.
One disadvantage of the existing bonding methods is that, after bonding, the bonding pad metal materials, such as copper, are exposed to air or other unprotected ambient environment in the open space between the dies. This problem can cause reliability concerns with the metal material bonding pads due to metal oxidation and corrosion in open-air or other harsh environments. This may be exacerbated by the fact that, in advanced technology, the dimensions of an inter-wafer bonding pad continue to decrease, while the density of the inter-wafer bonding pads increases significantly. There are generally hundreds or more of inter-wafer bonding pads in an integrated circuit having a three-dimensional stacked-die configuration.